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Quantum Analyzer


California, United States
Government : Federal
RFP
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I.UHFQA Quantum Analyzer
Real-time weighted averaging with 4kSa freely programmable filter memory :
1.Triggered acquisition with hardware averaging of up to 32k shots
2.Multiplication and integration of raw input signals at 1.8 GSa/s with filter memory

Simultaneous readout of 10 qubits on a single signal line using 10 weighted averaging units:
1.1 MSa memory for storage of readout results
2.Hardware averaging unit with up to 130k averages for processing of multi-qubit readout results


Real-time qubit readout crosstalk suppression:
1.Multiplication of input signals with configurable 2x2 deskew matrix
2.Multiplication of readout signals with configurable 10x10 matrix


Real-time multi-qubit state discrimination :
1.Feed-forward with latency <280 ns
2.Parallel digital output of readout results


Correlation of qubit readout measurement :
1.Multiplication of two arbitrary analog qubit readout signals
2.Multiplication of two arbitrary digital qubit readout signals


II. HDAWG Arbitrary Waveform Generator


Modulation with up to 16 digital oscillators :
1.Independent envelope waveforms for up to 8 oscillators can be added per output channel
2.Digital IQ modulation


Low latency :
1.Trigger-in to sample output <50ns
2.Dynamic sequencing with 10-bit input signal <150ns


The only AWG available with real-time precompensation:
1.Real-time operation for compatibility with dynamic sequencing (fast feedback)
2.1x high-pass filter, 10x exponential filters, 1x bounce correction, 1x FIR


III. PQCS Programmable Quantum System Controller

Up to 144 synchronized AWG channels:
1. Central clock and frequency reference control in a star-like network topology
2. Channel to channel skew <200ps


Serial real-time communication links with < 100 ns communication latency :
1. ZSync protocol for distribution of clock and data (qubit readout and dynamic waveform selection signals)
2. Timed execution of instructions on slave AWGs


Combines multiple HDAWG and UHFQA to the only Quantum Computing Control System (QCCS) with a central control architecture:
1.Dedicated FPGA for central processing of qubit readout results
2.Status monitoring of master and slave devices


 


Alan Chan, Principal Subcontracts Administrator, Phone 5104866768, Email alanchan@lbl.gov

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